1. Field of the Invention
The present invention relates to an information processing apparatus including a wide IO memory device stacked on an SoC die that includes a CPU.
2. Description of the Related Art
In information processing apparatuses that include a CPU such as a microprocessor, a DRAM is often used for storage of data for executing an OS and various applications, and for temporary storage of data for executing image processing. The DRAM is connected to a CPU, an SoC (System on a Chip), or the like and used by them. Furthermore, in recent years, as functions have been added/enhanced in information processing apparatuses, the amount of memory bandwidth needed in DRAMs has increased. Because of this, the amount of memory bandwidth has been increased by raising the clock frequency during memory access, according to a standard such as DDR3 or DDR4. Furthermore, as another method, memory bandwidth is reserved by including multiple DRAM channels that are connected to a CPU or an ASIC (Application Specific Integrated Circuit). However, a new problem occurs in that increasing the clock frequency and employing multiple memory channels increases power consumption.
In view of this, wide IOs, which are a next-generation DRAM standard, are currently gaining attention. A wide IO is configured by placing a DRAM chip over an SoC die using a 3D stacking technique based on TSVs (Through-Silicon Vias). Features of the wide IO include being able to obtain a wide bandwidth that is over 12.8 GB/s (gigabytes per second) at most, with a wide data width of 512 bits, and having low power consumption due to the access frequency being suppressed, to a low frequency. Also, by employing TSVs, the package size can be made thinner and smaller compared to a conventional PoP (Package on Package). Furthermore, as a counter-measure against heat caused by stacking memories in an SoC package, a temperature sensor that, detects the memory temperature is built, in, and the self-refresh rate is changed according to the detected temperature. Also, in this configuration, a data width of 512 bits is divided into four 128-bit channels and each channel is controlled individually. For example, a method of use is possible in which channel 1 and channel 2 are put in a self-refresh state, while channel 3 and channel 4 are used for normal memory access, or the like. A basic structure and basic access method for such a wide IO is disclosed in US2012/0018885.
On the other hand, there has been increased, demand to reduce the amount of CO2 emissions in the interest of preventing global warming, as well as demand, to lower the power consumption of information processing apparatuses, exemplified by MFPs (digital multifunction devices), which have multiple functions, such as image scanning, printing, and copying. A power-saving mode has conventionally been provided in MFPs in order to achieve low power consumption. This power saving mode achieves low power consumption by stopping the supply of power to areas that do not operate during standby in a state in which processing such as printing is not performed. Additionally, a power saving mode capable of shortening the time for returning from the power saving mode to the normal mode has also been implemented. Specifically, a suspend mode is employed, which lowers the power consumption of the MFP with the below-described procedures (A) and (B).
(A) State data (register, RAM data, etc.) that indicates the operating state of the CPU, the RAM, and the like is stored in a RAM that is in a self-refresh state.
(B) The supply of power to, for example, a RAM that is not a self-refresh target, is stopped.
A return from the suspend mode to the normal mode is performed due to the CPU receiving an interrupt due to some kind of return trigger (the press of an operation panel button, or a periodic startup caused by a timer) or the like. In the case of a return to the normal mode, the return time is shortened by returning the state data that indicates the operating state of the CPU, the RAM, and the like, and that had been stored in the RAM in the self-refresh state up to that time, to the location (RAM) in which it was stored before transitioning to the suspend mode, and then resuming processing.
The stacked structure of a wide IO is structurally susceptible to heat. For example, if a specific region of a SoC die and a DRAM chip of a wide IO placed on a layer above this specific region are activated, at the same time, the temperature of the activated portions sometimes rises locally. This rise in temperature is accompanied by an exponential increase in leak current in the semiconductor and an increase in power consumption. In addition, the DRAM performs storage of data by storing charge in a capacitor included in each cell. Since the capacitors are naturally discharged by leak current in the semiconductor, it is necessary for the DRAM to charge the capacitors by performing a refresh operation, in order to preserve the stored data. The discharging of this charge depends on the temperature of the DRAM, and the higher the temperature is, the faster the discharge speed is. Accordingly, if the temperature of the DRAM becomes high, the refresh frequency needs to be increased. As a result, this invites an increase in power consumption caused by refresh operations. This causes an increase in power consumption in the suspend mode, which accounts for a large portion of the power consumption of the RAM in the self-refresh state.